1. Field of the Invention
This invention relates generally to junction field effect transistors (JFETs) and in particular to a new process for forming a high power high frequency JFET that has an improved breakdown voltage control, reduced on-resistance, and overdrive capability.
2. Prior Art
One goal common to most microwave semiconductor manufacturers is to continually increase the maximum continuous wave (CW) power available from singularly packaged transistors. Recently, as a response to this demand for high performance power transistors, device designers and application engineers have directed their attention away from bipolar power transistors to field effect transistors (FETs). As a consequence, while bipolar transistors have experienced incremental performance gains, FETs, both in MOS and junction gate configurations, have made large steps forward in electrical performance, reliability levels, and cost competitiveness.
For very high radio frequency (RF)/microwave power generation and amplification, the use of a high power supply voltage is highly desirable. As higher power supply voltages are used, the current decreases and the transistor's specific impedance level increases, which in turn reduces the matching, combining, and power splitting circuitry loss and complexity. The higher impedance level makes wide operating frequency bandwidth achievable without significant trade offs in gain.
The power supply voltage for CW power transistors is limited by the transistor breakdown voltage. One technique used to permit higher power supply voltages to use a short channel JFET. One embodiment of a prior art short channel JFET 100 is illustrated in FIG. 1.
The drain of short channel junction field effect transistor (JFET) 100 is a heavily doped region 101 of conductivity type N++. Drain 101 is overlain by a lightly doped epitaxial layer 102 of conductivity type N-. As is known to those skilled in the art, a portion of region 102 functions as the channel of JFET 100.
Two pockets 103, 104 of conductivity type P+, with their centers separated by a distance "a" (the device pitch), extend into epitaxial region 102. Approximately centered between pockets 103, 104 in epitaxial region 102 is a doped source region 105 of conductivity type N+ or N++. An insulating layer 106 (in FIG. 1, a letter is used after reference numeral 106 to identify the different regions of the insulating layer that are visible in the cross-sectional view) overlies surface 102A and has contact openings over pockets 103, 104 and a contact opening over source 105.
Metal gate electrodes 110, 112 electrically contact pockets 103 and 104 respectively and overlie insulating layer 106 so that portions of electrodes 110 and 112 which are not in electrical contact with pockets 103 and 104 are electrically insulated from region 102. Source electrode 111 electrically contacts source 105 and also overlies insulating layer 106 so that portions of electrodes 111 which are not in electrical contact with source 105 are electrically insulated from region 102. A passivation layer 113 overlies electrodes 110, 111, 112 and insulating layer 106.
Short channel JFET 100 has non-saturated current voltage (I-V) characteristics which are similar to those of a vacuum tube triode. FIG. 2 is a graph of the I-V characteristics for short channel JFET 100. The ordinate of the graph is the drain-to-source current in amps (I.sub.DS [A]) the abscissa is the drain-to-source voltage in volts (V.sub.DS [V]). Curves 201, 202, 203, 204, and 205 are for gate-to-source voltages (V.sub.GS [V]) of 0, -2, -4, -6, and -8 volts respectively.
The drain current of JFET 100 (FIG. 1) is controlled by the (negative) gate potential, as well as the (positive) drain potential. The drain current decreases as the magnitude of the (negative) gate voltage increases. Moreover, the drain current increases with a rise in the drain voltage, a "short channel"-like behavior. Conditions under which semiconductor devices exhibit triode-like I-V characteristics are well-known to those skilled-in-the-art. For example see, G. F. Neumark, E. S. Rittner, "Transition from pentode- to triode-like characteristics in FETs", SSE, V10, pp. 299-304, 1967. Other references that define the prior art include: W. Shockley, "Transistorelectronics: imperfections, unipolar and analog transistors", PIRE. V40, pp. 1289-1313, November 1952; R. Zuleeg, "Multi-channel FET theory and experiment", SSE, V10, pp. 559-576, 1967; J. R. Houser, "Characteristics of JFET devices with small channel-to-width ratios", SSE, V10, pp. 577-587, 1967; C. Kim, E. Yang, "Carrier accumulation and space-charge-limited current flow in FETs", SSE, V13, pp. 1577-1589, 1970; J. Nishizawa, T. Terasaki, J. Shibata, "FET versus Analog Transistor (Static Induction Transistor)"; A. S. Wang C. J. Dell'Oca, "A compatible bipolar and JFET Process" IEDM Proc., pp. 45-47, December 1976; J. Nishizawa, "Semiconductor technology in Japan", North Holland, Publisher, N.Y., 1982; M. G. Kane, R. Frey, "The PSIFET emerges as a new contender", MSN, pp. 46-58, September 1984; A. Cogan, R. Blanchard, "Progress toward the ultimate semiconductor switch", Powertechniques Magazine, pp. 35-39, September 1986; J. Browne, "Solid State Triodes boost high voltages at broad bandwidths", Microwaves & RRF, pp. 211-224, May, 1989; B. J. Baliga, "Bipolar operation of power JFETs", EI.Letters, V10, No. 2, February 1980.
Short channel JFET 100 is a majority carrier device with high internal electric fields that exhibits a large number of favorable electrical and radio frequency characteristics (TABLE I). Only majority carriers (electrons) flow in the short channel of JFET 100 (FIG. 1). Hence, JFET 100 operates at high frequencies because no minority carrier effects are present to slow its operation.
TABLE I ______________________________________ Characteristics of Prior Art Short Channel JFET 100. ______________________________________ Blocking voltage &gt; 120 V. Voltage Gain .gtoreq. 25 @V.sub.DS = 40 V, I.sub.DS = 1 A. Transconductance .gtoreq. 400 mS at V.sub.DS = 50 V, I.sub.DS = 1 A. C.sub.GD .ltoreq. 0.3 pF/W @ V.sub.GD = 50 volts. C.sub.GS .ltoreq. 0.4 pF/W @ V.sub.DS = 15 volts. C.sub.DS .ltoreq. 0.1 pF/W @ V.sub.DS = 50 volts. Saturated CW power .gtoreq. 150 W @ 250 MHz. F.sub.mag .gtoreq. 4GHz. Power gain .gtoreq. 10db @ 250 MHz. Power (drain) Efficiency .gtoreq. 65% @ 500 MHz ______________________________________
While prior art short channel JFET 100 provides enhanced performance over equivalent bipolar and MOS transistors, short channel JFET 100 is limited by the on-resistance, power overdrive capability, and process limitations that affect breakdown voltage. Techniques for enhancing each of these characteristics are known, but the techniques are generally not applicable to high frequency high power short channel JFET 100. Specifically, the techniques degrade either or both of the power and frequency capability of JFET 100. Therefore, applications of JFET 100 are limited to those applications were the on-resistance, power overdrive and breakdown voltage limitations are not of concern. Unfortunately, in most high power high frequency applications, all of these factors are of concern.